Time-to-digital converters (TDC) are well known in the prior art. TDC circuits are currently widely used for time interval measurements in applications such as space science, high-energy physics, laser range finders and in test instrumentation. Recently, TDC circuits have been applied to frequency synthesis in delay locked loops (DLLs) to achieve faster acquisition and to avoid false locking. With the advent of digitally-intensive and all-digital fractional-N phase locked loops (PLLs) in deep-submicron CMOS, the TDC is becoming an attractive replacement of the conventional phase/frequency detector and charge pump. This also enables the replacement of the loop filter, typically requiring large and leaky integrating capacitors, with a simple digital filter.
Prior art TDC circuit architectures utilize an analog approach to first convert the time difference to a voltage and then to convert the voltage to a digital word using an analog to digital converter (ADC). More recent TDC circuit architectures use multiphase ring oscillators and delay locked loops to realize the interpolation of clock edges. The minimum time resolution of these prior art designs, however, is limited to a buffer delay. Other prior art TDC circuit architectures are based on a Vernier line and employ pulse-shrinking techniques. These two methods address the limitation of the coarse intrinsic delay of buffer elements and apply the gate delay difference to improve the resolution below the sub-gate delay. The above approaches, however, are less than ideal since they are analog intensive, require extensive calibration for high-volume production, suffer from long dead time and large power dissipation and require relatively large silicon area.
Thus, there is a need for a time-to-digital circuit architecture that (1) does not suffer from the disadvantages of prior art time-to-digital converters, (2) is well suited for implementation in deep-submicron CMOS processes, (3) takes advantage of the deep-submicron CMOS process strengths of ultra-fast logic switching, (4) avoids the weaker handling of voltage resolution of CMOS processes, (5) can be used as a phase/frequency detector replacement in an all digital PLL, and (6) is insensitive to NMOS and PMOS transistor mismatches.